The present invention relates to DMOS-type power transistors, and particularly to such transistors which provide vertical current flow.
Vertical-current DMOS-type power transistors have become an increasingly dominant technology for solid-state power-switching devices. In the basic technology of such transistors, a heavily doped n+ source region is separated from a surface extension of the drain (normally n-type) by a relatively narrow p-type channel region (which is normally outdiffused from the same pattern as the source diffusion). A gate (typically polysilicon) is capacitively coupled to the channel region to controllably invert it. When the channel is inverted, electrons flow from the source region through the channel into the surface extension of the drain, and thence downward through a drain conduction region to eventually reach an n+ drain. The drain may be at the back surface, or may be a buried layer in integrated power processes. The general characteristics of such devices are discussed in the following texts, all of which are hereby incorporated by reference: B. E. Taylor, POWER MOSFET DESIGN (1993); B. J. Baliga, MODERN POWER DEVICES (1987); Grant and Gowar, POWER MOSFETS: THEORY AND APPLICATIONS (1989); and E. Oxner, POWER FETS AND THEIR APPLICATIONS, (1982).
On-Resistance
The on-resistance per unit area of a MOS-gated power device is very important, since it determines the silicon area required to obtain a specified device resistance. However, there is a trade-off between breakdown voltage and on-resistance. Thus as the breakdown voltage of the device increases, the silicon area required to get the on-resistance down to a specific target value increases rapidly. See generally Darwish and Board, "Optimization of Breakdown Voltage and on-resistance of VDMOS transistors," 31 IEEE TRANS'NS ELECTRON DEVICES 1769 (1984), which is hereby incorporated by reference.
A number of techniques have been developed to minimize the on-resistance by increasing the doping concentration of the drain region below the gate. (If this added doping concentration is sufficiently light and shallow, it will not degrade the breakdown voltage of the device.) One technique uses lateral diffusion of dopants into the surface drain region; another uses implantation into the surface drain region.
Field-Plate-Induced Breakdowvn
One of the possible breakdown mechanisms in high-voltage MOS transistors is field-plate-induced breakdown, in which the potential on a field plate above a heavily doped region causes a "breakdown" in the heavily doped region, with a consequent high current flow between electrodes which contact the doped region. This effect is described and analyzed in Declercq and Plummer, "Avalanche breakdown in high-voltage D-MOS devices," 23 IEEE TRANSACTIONS ON ELECTRON DEVICES 1 (1976), which is hereby incorporated by reference.
As seen in FIGS. 3A1 and 3A2, the breakdown voltage (for a given oxide thickness under the field plate) therefore has a minimum value at some moderate level of doping, and increases at lower or high doping levels.
Optimal Spacing
For devices with high power-handling capability, many transistor cells are packed in an array. The lateral spacing between cells in the array therefore has a large influence on the overall current density which can be achieved. Published analyses have indicated that there is an optimal spacing, for a given set of device parameters, which will minimize on-resistance. Moreover, this spacing is dependent on the background doping seen at the surface of the VDMOS device.
FIG. 3B indicates the shape of the relation between breakdown voltage and lateral cell spacing, for two different values of body doping. As these curves show, the optimal spacing is lower for higher background dopant concentrations (at least within the range of background dopant concentrations which might be considered for normal device use). See generally Hu, "A Parametric Study of Power MOSFETS," IEEE POWER ELECTRONICS SPECIALISTS CONFERENCE RECORD 385 (1979).
Gate Capacitance of Power FETs
The gate of a large insulated-gate device is a lattice which may run over a very large area of silicon (particularly in discrete devices). In analyzing turn-on and turn-off of such devices, the RC time constant of the gate must be carefully considered: if the applied gate voltage is switched within a duration less than this time constant, then different parts of the gate may have significantly different transient voltage levels, and some parts of the transistor may be on while others are off. This may cause "hot-spotting" or other undesirable effects to occur.
The RC time constant of the gate can be reduced by making metal contact to the gate in more places. This effectively reduces the "R" term in the time constant. However, each such contact consumes some gate area. Moreover, in single-level-metal processes, the requirements of making source contacts severely constrain the possible geometries for gate contacts.
A large part of the gate capacitance is unavoidable, since the gate must be closely coupled to the channel in order for the transistor to operate. However, the channel is only a small fraction of the surface area, and gate coupling to the source and body regions is not particularly necessary. (The source and body areas all have relatively high dopant concentrations, and hence provide high capacitance per unit area where the gate is capacitively coupled to these regions.)
Innovative Processes and Structures
The present application discloses two modifications to the familiar DMOS structures and processes, which provide reduced on-resistance without increasing gate capacitance. These modifications are particularly advantageous in combination.
The first modification is a blanket shallow low-dose n-type implant at the surface of the device areas. This is preferably shallower than the source diffusion. This slightly counterdopes the channel region, so the concentration and/or diffusion length of the shallow p-type diffusion which surrounds the source can be slightly increased without degrading the transistor's on-resistance. This provides increased resistance to latchup in an integrated process (since the resistance of the intrinsic base of the parasitic npn is reduced).
A second modification is an added shallow n-type dopant contribution at the drain surface, which is preferably self-aligned to a LOCOS oxide. This combination provides several benefits:
1) The additional drain surface doping provides improved conductivity without degrading the breakdown voltage of the device. PA0 2) Since the LOCOS oxide separates the gate from most of the drain diffusion, capacitive loading on the gate is minimized. PA0 3) Lateral spacing between adjacent transistor cells is improved. PA0 4) The added drain surface dopant follows the curve of the LOCOS oxide, which provides some downward extension while still using a very shallow diffusion profile. (A deeper dopant profile, due either to deeper implantation or longer diffusion length, would risk some degradation of the voltage stand-off capability of the drain conduction region due to the lower-depth extension of the dopant distribution.)
To avoid field-plate-induced breakdown, both of the added doping contributions provide relatively small additional contributions (preferably a few times the background level), as detailed below.